Evolving wireless communication standards place increasingly stringent performance requirements on the frequency synthesizers that generate RF local oscillator signals for up and down conversion in wireless transceivers. Conventional analog fractional-N PLLs with digital delta-sigma (As) modulation are the current standard for such frequency synthesizers because of their excellent noise and spurious tone performance. See, e.g., T. A. Riley, M. A. Copeland, T. A. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis,” IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553-559, May 1993. Unfortunately, they require high-performance analog charge pumps and large-area analog filters, so the trends of CMOS technology scaling and increasingly dense system-on-chip integration have created an inhospitable environment for them.
Digital fractional-N PLLs have been developed over the last decade to address this problem. See, e.g., C. Hsu, M. Z. Straayer, M. H. Perrott, “A Low-Noise, Wide-BW 3.6 GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation,” IEEE International Solid-State Circuits Conference, pp. 340-341, February 2008. They avoid large analog loop filters and can tolerate device leakage and low supply voltages which makes them better-suited to highly-scaled CMOS technology than analog PLLs. They are increasingly used in place of analog PLLs as frequency synthesizers, but they have yet to fully replace analog PLLs in high-performance wireless applications. While both analog and digital fractional-N PLLs introduce quantization noise, in prior digital PLLs the quantization noise has higher power or higher spurious tones than in comparable analog PLLs. Consequently, they exhibit worse phase noise or spurious tone performance than the best analog PLLs. See, e.g., K. Wang, A. Swaminathan, I Galton, “Spurious-Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL,” IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2787-2797, December 2008. Digital PLLs based on second-order ΔΣ frequency-to-digital conversion (FDC-PLLs) offer a potential solution to this problem in that their quantization noise ideally is equivalent to that of an analog PLL with second-order ΔΣ modulation. To the knowledge of the inventors, prior second-order FDC-PLLs incorporate charge pumps and ADCs. See, e.g., W. T. Bax, M. A. Copeland, “A GMSK Modulator Using a ΔΣ Frequency Discriminator-Based Synthesizer,” IEEE Journal of Solid-State Circuits, vol. 36, no. 8, pp. 1218-1227, August 2001; C. Venerus, I. Galton, “Delta-Sigma FDC Based Fractional-N PLLs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 5, pp. 1274-1285, May 2013. The inventors have identified the charge pumps and ADCs in such prior second-order frequency-to-digital phase locked loops (FDC-PLLs) as placing limitations on performance and minimum supply voltage.